Semiconductor device and method of fabricating the same

ABSTRACT

A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member; a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2007-256354, filed on Sep. 28,2007, the entire contents of which are incorporated herein by reference.

BACKGROUND

In a wiring structure of a semiconductor device, an etching stopper filmis generally used for equalizing the depth when forming a wiring trench,a via hole or the like by etching and for inhibiting overetching to aninterlayer insulating film which is a lower layer (for example,disclosed in Japanese Patent Laid-Open No. 2006-19480).

BRIEF SUMMARY

A semiconductor device according to one embodiment includes: asemiconductor substrate provided with a semiconductor element; a firstconductive member formed on the semiconductor substrate; a firstinsulating film formed on the same layer as the first conductive member;a second conductive member formed so as to contact with a portion of anupper surface of the first conductive member; a second insulating filmformed on the first insulating film so as to contact with a portion ofthe upper surface of the first conductive member, and including at leastone type of element among elements contained in the first insulatingfilm except Si; and an etching stopper film formed on the secondinsulating film so as to contact with a portion of a side surface of thesecond conductive member, and having an upper edge located below theupper surface of the second conductive member.

A semiconductor device according to another embodiment includes: asemiconductor substrate provided with a semiconductor element; a firstconductive member formed on the semiconductor substrate; a firstinsulating film formed on the same layer as the first conductive member;a second conductive member formed so as to contact with a portion of anupper surface of the first conductive member; a second insulating filmformed on the first insulating film so as to contact with a portion ofthe upper surface of the first conductive member; and an etching stopperfilm formed on the second insulating film so as to contact with aportion of a side surface of the second conductive member, having anupper edge located below the upper surface of the second conductivemember, and a permittivity higher than that of the second conductivemember.

A method of fabricating a semiconductor device according to anotherembodiment includes: forming a first insulating film on a semiconductordevice provided with a semiconductor element; forming a first conductivemember in the first insulating film; forming a second insulating film onupper surfaces of the first insulating film and the first conductivemember; sequentially forming an etching stopper film and a thirdinsulating film on the second insulating film; forming a trench byetching the third insulating film so as to expose the etching stopperfilm; deepening the trench so as to expose the first conductive memberby removing the etching stopper film and the second insulating filmlocated under the trench; and forming a second conductive member in thetrench which is deepened.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view of a semiconductor device according toa first embodiment;

FIG. 2A and FIG. 2B are cross sectional views of the semiconductordevice according to the first embodiment when a cut surface taken online II-II of FIG. 1 is viewed in a direction indicated by an arrow inthe figure;

FIG. 3A and FIG. 3B are enlarged partial views of the semiconductordevice according to the first embodiment and a semiconductor device as acomparative example;

FIG. 4A to FIG. 4I are cross sectional views showing processes forfabricating the semiconductor device according to the first embodiment;

FIG. 5 is a cross sectional view of the semiconductor device accordingto a second embodiment;

FIG. 6 is a cross sectional view of the semiconductor device accordingto a third embodiment;

FIG. 7A and FIG. 7B are cross sectional views of the semiconductordevice according to the third embodiment when a cut surface taken online VII-VII of FIG. 6 is viewed in a direction indicated by an arrow inthe figure;

FIG. 8 is a cross sectional view of the semiconductor device accordingto a fourth embodiment;

FIG. 9A and FIG. 9B are cross sectional views of the semiconductordevice according to the fourth embodiment when a cut surface taken online IX-IX of FIG. 8 is viewed in a direction indicated by an arrow inthe figure;

FIG. 10 is a cross sectional view of the semiconductor device accordingto a fifth embodiment;

FIG. 11 is a cross sectional view of the semiconductor device accordingto a sixth embodiment;

FIG. 12 is a cross sectional view of the semiconductor device accordingto a seventh embodiment; and

FIG. 13A to FIG. 13C are cross sectional views showing processes forfabricating the semiconductor device according to the seventhembodiment.

DETAILED DESCRIPTION First Embodiment

FIG. 1 is a cross sectional view of a semiconductor device according toa first embodiment. Furthermore, FIG. 2A and FIG. 2B are cross sectionalviews when a cut surface taken on line II-II of FIG. 1 is viewed in adirection indicated by an arrow in the figure.

A semiconductor device 1 has a semiconductor substrate having asemiconductor element on a surface thereof and a multilayer wiringstructure laminated on the semiconductor substrate. FIG. 1 is a crosssectional view showing a portion of this multilayer wiring structure.

The semiconductor device 1 has a connecting portion 2, a contact 4electrically connected to the connecting portion 2, a contact layerinsulating film 3 formed on the same layer as the contact 4, a wiring 8formed on the contact 4 so as to contact with a portion of an uppersurface of the contact 4, an additional insulating film 5 formed on thecontact layer insulating film 3 so as to contact with a portion of theupper surface of the contact 4 and a portion of a side surface of thewiring 8 and comprising the same material as the contact layerinsulating film 3, an etching stopper film 6 formed on the additionalinsulating film 5 so as to contact with a portion of the side surface ofthe wiring 8 and having an upper edge located below an upper surface ofthe wiring 8, a wiring layer insulating film 7 formed on the etchingstopper film 6 so as to contact with the side surface of the wiring 8,and a cap layer 9 formed on the upper surface of the wiring 8 and thewiring layer insulating film 7. Note that, a layout of the contact 4,the wiring 8 or the like is not limited to that shown in FIG. 1.

The connecting portion 2 is a contact portion of a semiconductorsubstrate, a semiconductor element or the like. Concretely, it is acontact portion of a source/drain region or a gate electrode, forexample.

The wiring 8 comprises, for example, a conductive material such as Cu orthe like. Note that, the wiring 8 may have a structure having a barriermetal on the surface thereof for preventing diffusion of metals in thewiring 8. The barrier metal comprises, for example, a metal such as Ta,Ti, W, Ru, Mn or the like, or compounds of these metals.

The contact 4 comprises, for example, a conductive material such as W,Cu, Al or the like. Similarly to the wiring 8, the contact 4 may have astructure having a barrier metal on the surface thereof for preventingdiffusion of metals in the contact 4. Furthermore, a cross-sectionalshape of the contact 4 may be a nearly perfect circle as shown in FIG.2A or an elliptical shape as shown in FIG. 2B.

The contact layer insulating film 3 comprises, for example, TEOS(Tetraethoxysilane) or Si oxide such as SiO₂, SiOC which is C-dopedSiO₂, SiON which is N-doped SiO₂, SiOF which is F-doped SiO₂, BPSG whichis B and P-doped SiO₂ or the like. Furthermore, an organic insulatingmaterial such as SiOCH, polymethylsiloxane, polyarylene, benzoxazole orthe like may be used.

For a material of the wiring layer insulating film 7, it is possible touse the same material as the contact layer insulating film 3.

The etching stopper film 6 comprises an insulating material such as SiN,SiC, SiOC, SiCN, SiON or the like. Furthermore, since the etchingstopper film 6 functions as an etching stopper when etching the wiringlayer insulating film 7, it is preferable that the material of theetching stopper film 6 has a high etching selectivity with respect tothe wiring layer insulating film 7.

Since the etching stopper film 6 and the contact layer insulating film 3are formed of different materials, misfit, crystal defects, unstableconnecting bond or the like which may be a diffusion path of electronare present on an interface between them. Therefore, a leak current islikely to occur on the interface between the etching stopper film 6 andthe contact layer insulating film 3. In addition, breakdown is likely tooccur when applying high voltage. Meanwhile, since the additionalinsulating film 5 and the contact layer insulating film 3 comprise thesame material, there is less misfit on the interface between them,crystal defects decrease and connecting bond which was unstable isterminated on the same film. Furthermore, since adhesiveness of theinterface is improved, these problems are unlikely to occur.

FIG. 3A is an enlarged partial view of the wiring 8 of the semiconductordevice 1 according to this embodiment. In a miniaturized wiringstructure, a displacement (or misalignment) between a position in whichthe wiring is formed and a position in which the contact is formed oftenoccurs due to a problem such as matching accuracy of lithography. In thesemiconductor device 1 according to this embodiment, there is adisplacement between a position in which the wiring 8 is formed and aposition in which the contact 4 is formed, and a distance between thecontact 4 and the adjacent wiring 8 becomes shorter than a distancebetween the adjacent contacts 4 and a distance between the adjacentwirings 8. As a result, the distance between the contact 4 and theadjacent wiring 8 becomes a distance of closest approach L betweenadjacent conductive members (a pair of the wiring 8 and the contact 4).

FIG. 3B shows a wiring structure when directly forming the etchingstopper film 6 on the upper surfaces of the contact layer insulatingfilm 3 and the contact 4 without forming the additional insulating film5. In this case, as shown in FIG. 3B, since the distance of a pathpassing through the interface between the etching stopper film 6 and thecontact layer insulating film 3 which comprises different materials isthe distance of closest approach L, it is likely to become a leakcurrent pathway and the breakdown is likely to occur when applying highvoltage. Furthermore, since the upper rim of the contact 4 is a corner 4a to which electric field is likely to be focused and the interfacebetween the etching stopper film 6 and the contact layer insulating film3 directly contacts with this corner 4 a, the leak current and thebreakdown are likely to occur.

In the semiconductor device 1 according to this embodiment, as shown inFIG. 3A, the distance of closest approach L is not an interface betweenthe members comprising different materials due to an existence of theadditional insulating film 5 between the contact layer insulating film 3and the etching stopper film 6 and between the contact 4 and the etchingstopper film 6, misfit or crystal defects or the like decrease andadhesiveness is improved, thus, it is possible to prevent the leakcurrent and the breakdown is unlikely to occur even if higher voltage isapplied. Furthermore, since the corner 4 a of the contact does notcontact with the interface between the members comprising differentmaterials, it is possible to inhibit the generation of the leak currentand the breakdown in the same way.

Note that, it is preferable that the additional insulating film 5 has athickness of 3 nm or more for effectively inhibiting the generation ofthe leak current and the breakdown. It is because a uniform and stablefilm can be formed in a wafer plane by forming a film with a thicknessof 3 nm or more.

The cap layer 9 comprises an insulating material such as SiC, SiOC, SiNor the like.

An example of the processes for fabricating the semiconductor device 1according to this embodiment will be described hereinafter.

FIG. 4A to FIG. 4I are cross sectional views showing processes forfabricating the semiconductor device according to the first embodiment.

Firstly, as shown in FIG. 4A, after depositing the contact layerinsulating film 3 on the connecting portion 2 by a CVD (Chemical VaporDeposition) method or the like, for example, this deposited film ispatterned by a photolithographic method and an RIE (Reactive IonEtching) method, which results in that a contact hole 4 b for thecontact 4 is formed.

Next, as shown in FIG. 4B, a contact material 4 c is formed in thecontact hole 4 b. For example, when using W for the contact material 4c, for example, after forming a TiN film as a barrier metal by the CVDmethod, W is formed by the ALD (Atomic Layer Deposition) method or theplasma CVD method.

Next, as shown in FIG. 4C, the upper excess portion of the contactmaterial 4 c is removed by applying planarization treatment such as CMP(Chemical Mechanical Polishing) or the like, which result in that thecontact 4 is formed.

Next, as shown in FIG. 4D, the additional insulating film 5 is formed onthe contact layer insulating film 3 and the contact 4 by the CVD methodor the like. Note that, although the additional insulating film 5 isformed of a material substantially same as that of the contact layerinsulating film 3, a formation method may be different. Furthermore,mismatches may be generated between chemical composition ratio ofmaterials of the additional insulating film 5 and that of the contactlayer insulating film 3 in accordance with the difference of theformation method, the materials of them are regarded as substantiallysame. For example, when the contact layer insulating film 3 and theadditional insulating film 5 are SiO₂ films, it is possible to form bythe plasma CVD method using TEOS gas, or the plasma CVD method, thethermal oxidation method, the ALD method or the like using SiH₄ gas, andwhen formed by the CVD method using TEOS gas, the composition ratio of Oof SiO₂ may be shifted from 2. As an example, it is possible to form thecontact layer insulating film 3 by the plasma CVD method using SiH₄ gasand to form the additional insulating film 5 by the plasma CVD methodusing TEOS gas.

Next, as shown in FIG. 4E, the etching stopper film 6 and the wiringlayer insulating film 7 are sequentially formed on the additionalinsulating film 5 by the CVD method or the like.

Next, as shown in FIG. 4F, a wiring trench 8 a for the wiring 8 isformed by, for example, patterning the wiring layer insulating film 7 bythe photolithographic method and the RIE method. At this time, the depthof the wiring trench 8 a is equalized by the etching stopper film 6.

Next, as shown in FIG. 4G, the wiring trench 8 a is deepened by removingthe etching stopper film 6 and the additional insulating film 5 underthe wiring trench 8 a so as to expose at least a portion of the uppersurface of the contact 4. At this time, as shown in FIG. 4G, the contactlayer insulating film 3 is partially removed by displacement between theposition of the contact 4 and the position of the wiring trench 8 a, theremoved portion may be a portion of the wiring trench 8 a. Furthermore,by intentionally deepening the wiring trench 8 a, it is possible toimprove voltage endurance characteristics by extending a distancebetween a corner of a lower rim of the wiring 8 and the corner 4 a ofthe upper rim of the contact 4 to which electric field is likely to befocused.

Next, as shown in FIG. 4H, a wiring material 8 b is formed in the wiringtrench 8 a. For example, when using Cu as the wiring material 8 b, thewiring material 8 b is formed, for example, by forming a Ti or Ta filmas a barrier metal by a sputtering method or the like, sequentiallyforming a Cu seed film by the sputtering method, and then, plating a Cufilm thereon.

Next, as shown in FIG. 4I, the upper excess portion of the wiringmaterial 8 b is removed by applying a planarization treatment such asthe CMP or the like, which result in that the wiring 8 is formed. Afterthat, the cap layer 9 is formed on the wiring layer insulating film 7and the wiring 8 by the CVD method or the like.

According to the first embodiment, by forming the additional insulatingfilm 5 between the contact layer insulating film 3 and the etchingstopper film 6 and between the contact 4 and the etching stopper film 6,it is possible to prevent the distance of the path, which is passingthrough the interface between members comprising different materials,from becoming the distance of closest approach L, to inhibit thegeneration of the leak current and the breakdown, and to improveleak-resistant characteristics and voltage endurance characteristics.

Furthermore, in the same way, it is possible to inhibit the generationof the leak current and the breakdown, and to improve the leak-resistantcharacteristics and the voltage endurance characteristics by isolatingthe interface between the members comprising different materials fromthe corner 4 a of the contact 4 to which electric field is focused.

Second Embodiment

A second embodiment is different from the first embodiment in that anadditional insulating film 10 comprising a material different from thatof the contact layer insulating film 3 is used as an additionalinsulating film. The explanation will be omitted for the points same asthe first embodiment.

FIG. 5 is a cross sectional view of the semiconductor device accordingto the second embodiment.

The contact layer insulating film 3 comprises, for example, Si oxidesuch as SiO₂, SiOC which is C-doped SiO₂, SiON which is N-doped SiO₂,SiOF which is F-doped SiO₂, BPSG which is B and P-doped SiO₂ or thelike.

For a material of the additional insulating film 10, it is possible touse a material having permittivity lower than that of the etchingstopper film 6. It is possible to reduce electric field concentration onthe interface between the additional insulating film 10 and the contactlayer insulating film 3 by using a material having low permittivity as amaterial of the additional insulating film 10, hence, it is possible toimprove the leak-resistant characteristics and the voltage endurancecharacteristics of the semiconductor device 1. Therefore, compared withthe case that the etching stopper film 6 is provided at a position forthe additional insulating film 10, it is possible to lessen the electricfield concentration on the interface with the contact layer insulatingfilm 3 by using a material having permittivity lower than that of theetching stopper film 6. For example, when using SiN for the etchingstopper film 6, SiON, SiOC, SiCN, a low-K material or the like havingpermittivity lower than SiN are used for the additional insulating film10.

Furthermore, as a material of the additional insulating film 10, it isalso possible to use a material having strong bonding strength betweenatoms contained in both of the additional insulating film 10 and thecontact layer insulating film 3 on the interface thereof. For example,when using an Si compound film containing O such as SiO₂ or the like asthe contact layer insulating film 3, it is possible to use an Sicompound film containing O such as SiON, SiOC or the like as theadditional insulating film 10. As a result, a strong bonding isgenerated between an SiO₂ film and an SiON film via O, and the bondingstrength between the atoms contained in both of the additionalinsulating film 10 and the contact layer insulating film 3 on theinterface thereof is strengthened, hence, it is possible to improve theleak-resistant characteristics and the voltage endurance characteristicsof the semiconductor device 1.

Furthermore, in the same way, when using an Si compound film containingC such as an organic insulating material or the like as the contactlayer insulating film 3, it is possible to use an Si compound filmcontaining C such as SiCN, SiOC or the like as the additional insulatingfilm 10.

Namely, in order to enhance the bonding strength between the atomscontained in both of the contact layer insulating film 3 and theadditional insulating film 10 on the interface thereof, it is preferablethat common elements except Si are contained in the material of theboth. Furthermore, the bonding strength between the atoms contained inboth of the contact layer insulating film 3 and the additionalinsulating film 10 on the interface thereof is preferably stronger thanthe bonding strength between the atoms contained in both of the etchingstopper film 6 and the contact layer insulating film 3 on the interfacethereof when directly forming the etching stopper film 6 on the contactlayer insulating film 3.

According to the second embodiment, in the same way as the firstembodiment, it is also possible to obtain the semiconductor device 1having high leak-resistant characteristics and high voltage endurancecharacteristics when using a material different from that of the contactlayer insulating film 3 for the additional insulating film 5.

Third Embodiment

A third embodiment is different from the first embodiment in a layout ofthe contact 4. The explanation will be omitted for the points same asthe first embodiment.

FIG. 6 is a cross sectional view of the semiconductor device accordingto the third embodiment. Furthermore, FIG. 7A and FIG. 7B are crosssectional views when a cut surface taken on line VII-VII of FIG. 6 isviewed in a direction indicated by an arrow in the figure.

Although the shape of the contact 4 may be a nearly perfect circle asshown in FIG. 7A or an elliptical shape as shown in FIG. 7B, a pluralityof adjacent contacts 4 are arranged to shift each other in a lengthdirection of the wiring 8 without being arranged in a row. According tosuch arrangement, it is possible to increase the distance between theadjacent contacts 4. Furthermore, lithography resolution is improved byalternately arranging the contacts 4, and it is capable of forming thecontact 4 further smaller in size.

However, when the distance between the contact 4 and the adjacent wiring8 is the distance of closest approach L as this embodiment, theleak-resistant characteristics and the voltage endurance characteristicsare determined between the wiring and the contact even if the distancebetween the adjacent contacts 4 are increased, therefore, it isdifficult to greatly improve the leak-resistant characteristics and thevoltage endurance characteristics only by separating the contacts.Therefore, even when the contact is formed in such layout, it ispossible to improve the leak-resistant characteristics and the voltageendurance characteristics by adopting the wiring structure using theadditional insulating film 5, in the same way as the first embodiment.

According to the third embodiment, since the leak-resistantcharacteristics and the voltage endurance characteristics between thewiring and the contact are improved, it is possible to obtain the sameeffect as the first embodiment even when the layout of the contact 4 isdifferent from that of the first embodiment.

Fourth Embodiment

In a fourth embodiment, a width of the contact 4 with respect to thewiring 8 is larger than that of the first embodiment. The explanationwill be omitted for the points same as the first embodiment.

FIG. 8 is a cross sectional view of the semiconductor device accordingto the fourth embodiment. Furthermore, FIG. 9A and FIG. 9B are crosssectional views when a cut surface taken on line IX-IX of FIG. 8 isviewed in a direction indicated by an arrow in the figure.

The shape of the contact 4 may be a nearly perfect circle as shown inFIG. 9A or an elliptical shape as shown in FIG. 9B, however, the widthof the adjacent contacts 4 with respect to that of the wiring 8 islarger than that of the first embodiment. In such case, the distancebetween the adjacent contacts 4 is shorter than the distance between theadjacent wirings 8 and the distance between the contact 4 and theadjacent wiring 8, and becomes the distance of closest approach betweenthe adjacent conductive members.

Even in such case, when the additional insulating film 5 is not formed,the distance of the path passing through the interface between theetching stopper film 6 and the contact layer insulating film 3 becomesthe distance of closest approach between the adjacent conductivemembers, and the leak current and the breakdown are much more likely tooccur. Therefore, it is possible to improve the leak-resistantcharacteristics and the voltage endurance characteristics by adoptingthe wiring structure using the additional insulating film 5 in the sameway as the first embodiment.

According to the fourth embodiment, it is possible to obtain the sameeffect as the first embodiment by forming the additional insulating film5 even when the distance between the adjacent contacts 4 is the distanceof closest approach between the adjacent conductive members.

Fifth Embodiment

A fifth embodiment is different from the first embodiment in theposition where the additional insulating film 5 is formed. Theexplanation will be omitted for the points same as the first embodiment.

FIG. 10 is a cross sectional view of the semiconductor device accordingto the fifth embodiment.

A semiconductor device 11 has a wiring 8, a wiring layer insulating film7 formed on the same layer as the wiring 8, a via 12 formed on thewiring 8 and electrically connected to the wiring 8, an additionalinsulating film 5 formed on the wiring layer insulating film 7 so as tocontact with a portion of an upper surface of the wiring 8 as well as aportion of a side surface of the via 12 and comprising the same materialas the wiring layer insulating film 7, an etching stopper film 6 formedon the additional insulating film 5 so as to contact with a portion ofthe side surface of the via 12, and a via layer insulating film 13formed on the etching stopper film 6 so as to contact with the sidesurface of the via 12. Note that, a layout of the via 12, the wiring 8or the like is not limited to that shown in FIG. 10.

The via layer insulating film 13 comprises, for example, Si oxide suchas SiO₂, SiOC which is C-doped SiO₂, SiON which is N-doped SiO₂, SiOFwhich is F-doped SiO₂, BPSG which is B and P-doped SiO₂ or the like.

For a material of the wiring layer insulating film 7, it is possible touse the same material as the via layer insulating film 13. Furthermore,an organic insulating material such as SiOCH, polymethylsiloxane,polyarylene, benzoxazole or the like may be used.

The etching stopper film 6 comprises an insulating material such as SiN,SiC, SiOC, SiCN, SiON or the like. Furthermore, since the etchingstopper film 6 functions as an etching stopper when etching the vialayer insulating film 13, it is preferable that the material of theetching stopper film 6 has a high etching selectivity with respect tothe via layer insulating film 13.

The via 12 comprises, for example, a metal such as Cu, Al, Au, Ag, W orthe like. Note that, the via 12 may have a structure having a barriermetal on the surface thereof for preventing diffusion of metals in thevia 12. Furthermore, the cross-sectional shape of the via 12 may be anearly perfect circle or an elliptical shape.

In the semiconductor device 1 according to this embodiment, similarly tothe wiring 8 and the contact 4 in the first embodiment, there is adisplacement between the position in which the via 12 is formed and theposition in which the wiring 8 is formed, a distance between the wiring8 and the adjacent via 12 becomes shorter than a distance between theadjacent wirings. Therefore, the distance between the wiring 8 and theadjacent via 12 is a distance of closest approach between adjacentconductive members.

In the semiconductor device 1 according to this embodiment, since thedistance of the path passing through the interface between memberscomprising different materials is not the distance of closest approachbetween the adjacent conductive members due to an existence of theadditional insulating film 5 between the wiring layer insulating film 7and the etching stopper film 6 and between the wiring 8 and the etchingstopper film 6, it is possible to inhibit the generation of the leakcurrent and the breakdown when applying high voltage. Furthermore, sincea corner 8 c of the wiring 8 does not contact with the interface betweenmembers comprising different material, it is possible to inhibit thegeneration of the leak current and the breakdown, in the same way.

Note that, it is preferable that the additional insulating film 5 has athickness of 3 nm or more for effectively inhibiting the generation ofthe leak current and the breakdown. It is because a uniform and stablefilm can be formed in a wafer plane by forming a film with a thicknessof 3 nm or more.

According to the fifth embodiment, by forming the additional insulatingfilm 5 between the wiring layer insulating film 7 and the etchingstopper film 6 and between the wiring 8 and the etching stopper film 6,it is possible to prevent the distance of the path, which is passingthrough the interface between members comprising different materials,from becoming the distance of closest approach between the adjacentconductive members, to inhibit the generation of the leak current andthe breakdown, and to improve leak-resistant characteristics and voltageendurance characteristics.

Furthermore, in the same way, it is possible to inhibit the generationof the leak current and the breakdown, and to improve the leak-resistantcharacteristics and the voltage endurance characteristics by isolatingthe interface between the members comprising different materials fromthe corner 8 d of the wiring 8 to which electric field is focused.

Sixth Embodiment

A Sixth embodiment is different from the fifth embodiment in that anadditional insulating film is applied in consideration of wiring pitchesof other circuit regions or the like. The explanation will be omittedfor the points same as the fifth embodiment.

FIG. 11 is a cross sectional view of the semiconductor device accordingto the sixth embodiment. A semiconductor device 14 has a first region 20having a wiring in which a via is connected to the upper surface thereofand a distance between wirings is relatively large, and a second region30 having a wiring in which a via is not connected to the upper surfacethereof and a distance between wirings is relatively small.

The first region 20 includes a wiring 21, a wiring layer insulating film7 formed on the same layer as the wiring 21, a via 22 formed on thewiring 21 and electrically connected to the wiring 21, an additionalinsulating film 5 formed so as to contact with upper surfaces of thewiring 21 and the wiring layer insulating film 7 as well as the sidesurface of the via 22 and comprising the same material as the wiringlayer insulating film 7, an etching stopper film 6 formed on theadditional insulating film 5 so as to contact with the side surface ofthe via 22, and a via layer insulating film 13 formed on the etchingstopper film 6 so as to contact with the side surface of the via 22.Note that, a layout of the via 22, the wiring 21 or the like is notlimited to that shown in FIG. 11.

The second region 30 includes a wiring 31 formed on the same layer asthe wiring 21 of the first region 20, a wiring layer insulating film 7commonly formed with the first region 20, an additional insulating film5, an etching stopper film 6 and a via layer insulating film 13. Notethat, a layout of the via 31 or the like is not limited to that shown inFIG. 11.

In the first region 20, since the distance between the adjacent wiringsis relatively large, the leak current or the breakdown is not likely tooccur between the adjacent wirings or between the wiring and theadjacent via even if it is conventionally used structure in which theadditional insulating film 5 is not formed. However, since the etchingstopper film 6 is commonly formed also in the second region 30 in whichthe distance between the adjacent wirings is relatively small, if theadditional insulating film 5 is not formed, the leak current and thebreakdown during high-voltage application are likely to occur betweenthe adjacent wirings 31 via the interface between the etching stopperfilm 6 and the wiring layer insulating film 7.

Therefore, although the etching stopper film 6 is a required member whenprocessing the via layer insulating film 13 in the first region 20, itis formed on the additional insulating film 5 for preventing thegeneration of the leak current or the breakdown in the second region 30.

According to the sixth embodiment, by forming the etching stopper film 6required in the first region 20 on the additional insulating film 5, itis possible to prevent the distance of the path, which is passingthrough the interface between members comprising different materials,from becoming the distance of closest approach between the adjacentwirings 31, to inhibit the generation of the leak current and thebreakdown, and to improve the leak-resistant characteristics and thevoltage endurance characteristics of the semiconductor device 14.

Seventh Embodiment

A Seventh embodiment is different from the first embodiment in that arim of the upper portion of the contact 4 is rounded. The explanationwill be omitted for the points same as the first embodiment.

An example of the processes for fabricating the semiconductor device 1according to this embodiment will be described hereinafter.

FIG. 12 is a cross sectional view of the semiconductor device accordingto the seventh embodiment. The rim of the upper portion of the contact 4is a rounded portion 4 d without angles.

FIG. 13A to FIG. 13C are cross sectional views showing processes forfabricating the semiconductor device according to the seventhembodiment.

Firstly, the processes until the process, shown in FIG. 4C, for formingthe contact 4 are carried out in the same way as the first embodiment.

Next, as shown in FIG. 13A, an oxide region 14 is formed by applyingoxidation treatment to the upper surface of the contact 4. The oxideregion 14 is formed so that a region closer to the rim of the uppersurface of the contact 4 is deeper.

Next, as shown in FIGS. 13B, the oxide region 14 is removed by wetetching using aqueous solution of choline or the like. By removing theoxide region 14, the rim of the upper surface of the contact 4 becomesthe rounded portion 4 d which is round and without angles.

Next, as shown in FIG. 13C, the additional insulating film 5 is formedon the contact layer insulating film 3 and the contact 4 by the CVDmethod or the like.

After that, the processes after the process, shown in FIG. 4E, forforming the etching stopper film 6 and the wiring layer insulating film7 are carried out in the same way as the first embodiment.

According to the seventh embodiment, by making the rim of the uppersurface of the contact 4 to be a rounded portion 4 d, it is possible toprevent the electric field from focusing at the rim and to improve thevoltage endurance characteristics of the semiconductor device 1.

Other Embodiments

It should be noted that an embodiment is not intended to be limited tothe above-mentioned first to seventh embodiments, and the various kindsof changes thereof can be implemented by those skilled in the artwithout departing from the gist of the invention.

In addition, the constituent elements of the above-mentioned embodimentscan be arbitrarily combined with each other without departing from thegist of the invention.

1-7. (canceled)
 8. A method of fabricating a semiconductor device,comprising: forming a first insulating film on a semiconductor deviceprovided with a semiconductor element; forming a first conductive memberin the first insulating film; forming a second insulating film on uppersurfaces of the first insulating film and the first conductive member;sequentially forming an etching stopper film and a third insulating filmon the second insulating film; forming a trench by etching the thirdinsulating film so as to expose the etching stopper film; deepening thetrench so as to expose the first conductive member by removing theetching stopper film and the second insulating film located under thetrench; and forming a second conductive member in the trench which isdeepened.
 9. The method of fabricating a semiconductor device accordingto claim 8, wherein the second insulating film is formed using amaterial which contains at least one type of element among elementscontained in the first insulating film except Si.
 10. The method offabricating a semiconductor device according to claim 8, wherein thesecond insulating film is made of substantially same material as thefirst insulating film.
 11. The method of fabricating a semiconductordevice according to claim 9, wherein the first and second insulatingfilms contain at least one of O and C.
 12. The method of fabricating asemiconductor device according to claim 8, wherein the second insulatingfilm is formed using a material having a permittivity lower than that ofthe etching stopper film.
 13. The method of fabricating a semiconductordevice according to claim 12, wherein the etching stopper film is formedusing SiN; and the second insulating film is formed using one of SiON,SiOC, SiCN and a low-K material.
 14. The method of fabricating asemiconductor device according to claim 8, wherein a combination of thefirst and second conductive members is either a combination of a contactportion of a semiconductor device or a semiconductor element with acontact, a combination of a contact or a via with a wiring, or, acombination of a wiring with a via.
 15. The method of fabricating asemiconductor device according to claim 8, wherein an oxide region, inwhich a region closer to the upper rim is deeper, is formed by applyingoxidation treatment to the upper surface of the first conductive memberafter forming the first conductive member; and the upper rim of thefirst conductive member is processed into a rounded portion withoutangles by removing the oxide region.
 16. The method of fabricating asemiconductor device according to claim 8, wherein an upper surface ofthe first conductive member is provided in a substantially same verticalposition on an interface between the first insulating film and thesecond insulating film.
 17. The method of fabricating a semiconductordevice according to claim 8, wherein the trench is deepened by removingthe etching stopper film, the second insulating film and a portion ofthe first insulating film located under the trench.
 18. The method offabricating a semiconductor device according to claim 13, wherein thesecond insulating film is formed in the thickness of about 3 nm or more.19. The method of fabricating a semiconductor device according to claim8, wherein a plurality of the first conductive members and a pluralityof the second conductive members are formed at predetermined arrangingintervals, respectively, so that a distance between adjacent first andsecond conductive members is shorter than a distance between adjacentfirst conductive members and a distance between adjacent secondconductive members.
 20. The method of fabricating a semiconductor deviceaccording to claim 8, wherein a plurality of the first conductivemembers and a plurality of the second conductive members are formed atpredetermined arranging intervals, respectively, so that a distancebetween adjacent first conductive members is shorter than a distancebetween adjacent second conductive members and a distance betweenadjacent first and second conductive members.